As semiconductor devices have increasingly higher capacitances and faster operation speeds, the test time of semiconductor testers that test these devices is also required to become faster. Further, it is crucial that the optical semiconductor relay in the tester has a low capacitance and high operation speed. As means for achieving low capacitance and high operation speed characteristics in an optical semiconductor relay, various optical semiconductor relay devices are proposed (refer to Patent Documents 1, 2, and 3).
FIG. 3 is a circuit diagram of a solid-state relay of the type similar to these described in Patent Document 1 or a circuit diagram of an optically coupled relay device described in Patent Document 2 as a reference example. In FIG. 3, the optical semiconductor relay device comprises a pair of input terminals IN1 and IN2 and a pair of output terminals OUT1 and OUT2; a light-emitting diode (LED) that converts an input electrical signal supplied as a control signal into an optical signal is connected between the pair of the input terminals IN1 and IN2; and two MOSFETs N101 and N102 that turn on/off a load circuit connected externally are connected between the pair of the output terminals OUT1 and OUT2. Source electrodes and drain electrodes of the MOSFETs N101 and N102 are connected in anti-series (series in opposite direction) to each other so that the source electrodes are short-circuited with each other. The reason is as follows. In most cases, the optical semiconductor relay device has an AC signal flow between the output terminals OUT1 and OUT2, and in order to maintain an OFF state between the output terminals OUT1 and OUT2 in such cases, it is necessary to have a structure in which a reverse-blocking state can be bidirectionally maintained.
Further, a drive circuit 100 that drives the MOSFETs is provided between the LED D101 and the MOSFETs N101 and N102. The drive circuit 100 is formulated by a photodiode array FD 101 that receives light from LED D101 and converts it into an electrical signal, and a discharge circuit 101 provided so as to quickly discharge carriers accumulated on gate electrodes when the MOSFETs N101 and N102 perform an off-operation. The photodiode array FD11 is formulated by a plurality of photodiode elements connected in series and is characterized by an anode and a cathode of the photodiodes at both ends of the array.
Further, the discharge circuit 101 has a thyristor structure comprising a pnp transistor Q101 and an npn transistor Q102; a base electrode of the pnp transistor Q101 and the anode of the photodiode array FD11 are connected; and a base electrode of the npn transistor Q102 and the cathode of the photodiode array FD101 are connected. Further, diodes D102 and D103 that drive the pnp transistor Q101 and the npn transistor Q102, respectively, are connected between the base electrode and an emitter electrode of the respective transistor. The emitter electrode of the pnp transistor Q101 and a cathode of the diode D102 are connected to the gate electrodes of the MOSFETs N101 and N102, and the emitter electrode of the npn transistor Q102 and an anode of the diode D103 are connected to the source electrodes of the MOSFETs N101 and N102.
Next, the operation of the optical semiconductor relay device shown in FIG. 3 will be described. A current, as a control signal, flows between the anode and the cathode of the LED D101 constituting the input circuit. As a result, the LED D101 emits light, which is received by the photodiode array FD101. By receiving the light from the LED D101, the photodiode array FD101 generates a voltage, which causes a voltage exceeding a threshold voltage to be applied between the gate electrode and the source electrode of the MOSFETs N101 and N102 respectively. As a result, the MOSFETs N101 and N102 enter an ON state and so does the connection state between the output terminals OUT1 and OUT2. At this time, the discharge circuit 101, i.e., the thyristor, provided between the gate electrodes and the source electrodes of the MOSFETs N101 and N102, stays in an OFF state.
On the other hand, when no current is supplied to the LED D101, the photodiode array FD101 does not generate any voltage. At this time, the carriers accumulated on the gate electrodes of the MOSFETs N101 and N102 are urged to be discharged, however, since the diode D102 is connected reversely (as viewed from the gates of MOSFETs N101 and N102), only the leak current of the diode D102 and the thyristor (the pnp transistor Q101 and the npn transistor Q102) is discharged. Meanwhile, carrier recombination is under way inside the photodiode array FD101, which has lost the light, and the anode potential of the photodiode array FD101 decreases faster than the gate potential at the gate electrodes of the MOSFETs N101 and N102 does. As a result, when the potential difference between the anode potential of the photodiode array FD101 and the gate potential at the gate electrodes of the MOSFETs N101 and N102 exceeds the threshold voltage of the thyristor, the thyristor enters an ON state and the carriers accumulated on the gate electrodes of the MOSFETs N101 and N102 are discharged quickly via the thyristor. Further, when the gate-source voltage of the MOSFETs N101 and N102 becomes below the threshold voltage, the MOSFETs N101 and N102 enter an OFF state. As a result, the connection state between the output terminals OUT1 and OUT2 enters an OFF state.
In the conventional optical semiconductor relay device of the type as shown in FIG. 3, the drive circuit is constituted by a single circuit (single-circuit type). On the other hand, an optical semiconductor relay device of the type according to Patent Document 3, shown in FIG. 4, is a two-circuit type in which each of the MOSFETs N101 and N102 has a respective drive circuit in order to achieve a higher operation speed and low capacitance and each gate electrode is not short-circuited. In other words, in FIG. 4, a drive circuit 100a comprises the drive circuit constituted by the photodiode array FD101, the pnp transistor Q101, the npn transistor Q102, and the diodes D102 and D103 for the MOSFET N101; and the drive circuit constituted by a photodiode array FD102, a pnp transistor Q103, an npn transistor Q104, and diodes D105 and D106 for the MOSFET N102. These two drive circuits are the same circuits as the drive circuit shown in FIG. 3 and they operate identically.
It should be noted again that it is crucial for an optical semiconductor relay device to have low capacitance and high operation speed characteristics. In order to achieve this, the photodiode array and the discharge circuit are constituted using two circuits in the conventional optical semiconductor relay device of the type as shown in FIG. 4, and by having the photodiodes FD101 and FD102 drive the MOSFETs N101 and N102 respectively, high operation speed can be achieved.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-5-268042
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2004-260047A
[Patent Document 3]
Japanese Patent Publication No. JP3013894B